#ifndef __SPI_DRV_H__
#define __SPI_DRV_H__



//============================================================================
// 	
//	D E F I N A T I O N S 
//
//============================================================================
#define SPI_MAX_RX_BUFFER					(20)
#define SPI_MAX_TX_BUFFER					(20)

#define SPI_CHANNEL_SUPPORTED				(1)
#define SPI_CHANNEL_NOT_SUPPORTED			(0)



//------------------------------------------------------------------------------------
// definitions for TX/RX state  
//------------------------------------------------------------------------------------
#define SPI_RX_STATE_IDLE					(0)
#define SPI_RX_STATE_RECEIVE				(1)


#define SPI_TX_STATE_IDLE					(0)
#define SPI_TX_STATE_TRANSMIT				(1)




//------------------------------------------------------------------------------------
// definitions for read/write function 
//------------------------------------------------------------------------------------
#define SPI_TX_BUFFER_SUCCESS				(0)
#define SPI_TX_BUFFER_ERROR_WRONG_CHANNEL	(1)
#define SPI_TX_BUFFER_ERROR_WAIT_TIMEOUT	(2)

#define SPI_RX_BUFFER_SUCCESS				(0)
#define SPI_RX_BUFFER_ERROR_WRONG_CHANNEL	(1)
#define SPI_RX_BUFFER_ERROR_EMPTY			(2)





#define SPI_TXDATA_END_MARK					(0xFFFFFFFF)


//============================================================================
// 	
//	S T R U C T U R E S
//
//============================================================================
typedef struct {
	UINT16		u16RxState; 
	UINT16		u16TxState;
	
	UINT16		u16RxBuffer_HeadIndex;
	UINT16 		u16RxBuffer_TailIndex;
	
	UINT16		u16TxBuffer_HeadIndex;
	UINT16 		u16TxBuffer_TailIndex;
	
	UINT32		u32RxBuffer[SPI_MAX_RX_BUFFER];
	UINT32		u32TxBuffer[SPI_MAX_TX_BUFFER]; 

	UINT16		u16SCLK_count; 
} SPI_BUFFER; 







//============================================================================
// 	
//	E X T E R N    V A R I A B L E S 
//
//============================================================================
extern int 				g_SPI0_index; 
extern UINT32			g_SPI0_status[40];

extern int 				g_SPI1_index; 
extern UINT32			g_SPI1_status[40]; 


extern SPI_BUFFER		sSPI0_Master_Buffer; 
extern SPI_BUFFER		sSPI0_Slave_Buffer; 

extern SPI_BUFFER		sSPI1_Master_Buffer; 
extern SPI_BUFFER		sSPI1_Slave_Buffer; 




//============================================================================
// 	
//	D E C L A R A T I O N S
//
//============================================================================
int SPI_Init (int spi_no, int master_slave, int port_sel, SPI_CONFIG * p_config); 
CSP_SPI_T* SPI_Get_Object (int spi_no); 

int SPI_InitBuffer (int spi_no, int master_slave); 
SPI_BUFFER* SPI_Get_BufferAddr (int spi_no, int master_slave, int *p_result); 

int SPI_Write_Data (int spi_no, int master_slave, UINT32 *p_write_buf, UINT32 data_count); 
int SPI_Read_Data (int spi_no, int master_slave, UINT32 * p_read_buf, UINT32 * p_data_count); 


////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void SPI0_Master_Transmit_Receive_ISR(void); 
void SPI0_Slave_Transmit_Receive_ISR (void); 
void SPI1_Master_Transmit_Receive_ISR(void); 
void SPI1_Slave_Transmit_Receive_ISR (void); 

UINT32 SPI0_Master_Get_TX_Data_ISR (void); 
void SPI0_Master_Deposit_RX_Data_ISR (UINT32 rcv_data); 
UINT32 SPI0_Slave_Get_TX_Data_ISR (void); 
void SPI0_Slave_Deposit_RX_Data_ISR (UINT32 rcv_data); 



UINT32 SPI1_Master_Get_TX_Data_ISR (void); 
void SPI1_Master_Deposit_RX_Data_ISR (UINT32 rcv_data); 
UINT32 SPI1_Slave_Get_TX_Data_ISR (void); 
void SPI1_Slave_Deposit_RX_Data_ISR (UINT32 rcv_data); 



#endif 

